OP-FW10G Firmware for High-speed HDLC mode
Firmware for speeding up HDLC measurement to 10 Mbps for CC-link etc.Outline
OP-FW10G is an expansion firmware to upgrade LE-3500 measuring Bit-Synch (HDLC/SDLC/X.25/CC-Link) and SPI communications up to 10Mbps. Hardware processing by FPGA built in the analyzer makes it possible to capture data with time stamp at micro second. It is useful to analyze SPI communications and High-speed HDLC communications such as RS-485 multi-drop CC-LINK and TTL signal level on the printed-circuit board.
* To measure high-speed HDLC at TTL signal level and high-speed SPI with OP-SB5GL/OP-SB5G, you need to have OP-FW10G version 2.0 or later.
| Firmware | OP-FW10G | OP-FW10G |
|---|---|---|
| Version 2.00 or later | Version 1.00 | |
| RS-422/RS-485 HDLC | Supported | Supported |
| TTL/CMOS HDLC | Supported | No |
| TTL/CMOS, SPI | Supported | No |
Operating Instructions
RS-232C
Connect to RS-232C port of analyzer using the monitor cable “LE-25M1”.RS-422/485
Connect to RS-422/485 line as shown in the following figure by using the terminal block for DSUB 25-pin (LE-25TB) etc. of an option.
| Half-duplex | 2 (TxD_A), 14 (TxD_B) 7 Connect (GND) |
|---|---|
| Full-duplex | 2 (TxD_A), 14 (TxD_B) 3 (RxD_A), 16 (RxD_B) 7 Connect (GND) |
If you need the terminator, turn on by DIP SW on the interface board.
TTL
Connect using the optional expansion kit “OP-SB5G/OP-SB5GL”.<HDLC Monitor>  |
<HDLC Simulation> |
<SPI Monitor>  |
<SPI Simulation> |
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| * Master Mode Connect SDO(SD) to MOSI, SDI(RD) to MISO, SS(RTS) to SS, and SCK(TXC) to SCK.  |
*Slave Mode Connect SDO(SD) to MOSI, SDI(RD) to MISO, SS(RTS) to SS, and SCK(TXC) to SCK.  |
Monitoring
You can monitor network at arbitrary speed up to 10Mbps at real time. Time stamp resolution that is effective to check the response time can be selected from 1mS/100uS/10uS/1u. Therefore, it is useful for development and analysis of failures of high-speed communications effectively.HDLC/SDLC/X.25 and CC-Link
| It has raw data display, translation display at frame level, and translation display at packet level. ID filter can be individually specified up to 16 bits on the SD and RD side, and improve the efficiency of analysis. Furthermore, capture memory can be used effectively. |
<HDLC setup Screen> |
<HDLC monitor display (raw data)> |
<Translation display of HDLC> |
Description of ID filter
At the time of the half-duplex, the frame of a specific address can be divided to the SD side, the other frame can be divided to the RD side, and it can also display in detail.| ID filter setting: | SD-1 : 00110000 (30h) | RD-1 : 0100**** (don't care) |
| SD-2 : 00110001 (31h) | RD-2 : ******** (don't care) |
| Frames on TxD line |
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| Frames on RxD line |
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| ↓ | ||||||||||||||
| Monitored display on SD |
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| Monitored display on RD |
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Description of ID filter display when half duplex is "ON".
There are more than one nodes of frames when communicating at half duplex.Data will be displayed in one side line of the analyzer and is difficult to understand the communication frames.
By using the ID filter, it will divide the specific ID frames to the SD, and other frames will be displayed to the RD side.
| ID filter setting: | SD-1 : 00110000 (30h) | RD-1 : ******** (don't care) |
| SD-2 : 00110001 (31h)) | RD-2 : ******** (don't care) |
| Frames on TxD line |
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| Monitored display on SD |
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| Monitored display on RD |
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SPI
| It is able to support all four SPI transferring timing by setting of clock polarity and clock phase. It can analyze the relationship between transferring commands and data by setting the frame end time (resolution: 0.1us). This will divide data by frame end time and supports SPI devices which SS signal stays low level and transfer all frames. | <SPI setup Screen> |
<SPI monitor display (raw data)> |
<Dump display of SPI> |
Trigger
<Trigger setup Screen>
When 2 sets of data up to 8 characters (don’t care and bit mask available) is detected individually or sequentially, when error (CRC error, abort, short frame) is detected, or when status of external signal is changed, analyzer will stop monitoring automatically.
Simulation
<Standard Interface setup Screen>
<TTL Interface setup Screen>
Simulation function is useful when it is in initial stages of development, and when there is few counterpart which performs high-speed communication. <TTL Interface setup Screen>
By pressing the corresponded key, 16 kinds of data strings registered in the transmission data table can be transmitted once or repeatedly. When using RS-422/485 interface, it is possible to choose DTE/DCE and RS-485 automatic driver control.
When measuring TTL by OP-SB5GL/OP-SB5G (optional kits), it is possible to specify the output signal level and type, and able to test under the condition which suits to the power specification of target device.
Also for the SPI simulation, it is possible to choose the master/slave mode. If analyzer becomes the master mode, it can have high-speed data transmission/reception test up to 5Mbps.
Others
There is Auto-Save function which saves data to the external memory for long hours, text conversion function which converts data to the text format and print-out format, search function which retrieves specific data, and remote control function and so on. To return to the standard firmware, you can simply pressing [SHIFT]+[0] when turning on the power of analyzer.
Specification
| Applicable Analyzer | LE-3500 | |
|---|---|---|
| Interface | RS-422/ RS-485(RS-530)*1, TTL*2, SPI*2 | |
| Protocol | HDLC, SDLC, X.25, CC-Link (NRZ/NRZI format, AR clock), SPI | |
| Baud Rate | Half duplex | 115.2kbps to 10Mbps*3 |
| Full duplex | 115.2kbps to 5Mbps*3 | |
| Setting steps | Arbitrary: 4 digits | |
| Error Check | FCS error (CRC-ITU-T), abort, short frame | |
| Online Monitor | Time stamp | 6 digits: 0 to 524287 Resolution: 1ms, 100μs, 10μs, 1μs |
| ID Filter (HDLC) | Up to two characters (don't care and bit mask available) | |
| Simulation | Data Table | Up to 16K data (16 data table) |
| MANUAL mode | Transmit registerd data corresponded to key operation. | |
| Interval setting and repeat transmittion is available. | ||
| Trigger | When 2 sets of data string up to 8 characters (don't care and bit mask available) is detected individually or sequentially, or when error or low-level of external trigger is detected, monitoring action can be stopped automatically. | |
| Data Search | Search triggered data, error data, character strings. | |
| Composition | Firmware CD, Instruction Manual | |
*1: When using the standard board.
*2: Necessary to have OP-SB5GL or OP-SB5G.
*3: Necessary to have OP-SB5GL for high-speed TTL/ SPI Simulation.