OP-SB5G TTL/I²C Expansion Kit

Expansion board with probe pod for monitoring I²C and clock-synchronized TTL level communications. Ideal for onboard probing connections for monitoring communications between LSIs.

Outline

OP-SB5G is the interface expansion kit equipped with two kinds of the ports to measure communication: RS-232C (V.24) and TTL/C-MOS signal level. In TTL/C-MOS measurement, the communication line of TTL/C-MOS level between LSI and interface IC, power supply system 3V or 5V, is connected with the IC clip. Then, communication state can be monitored, and also the response can be checked outputting data.
Moreover, communication state of two-wires synchronized I²C can be monitored. Also, your analyzer operates as slave or master, and you can input/output data. In addition, you can use the burst measurement mode, which can capture all data.

Operating Instructions

After inserting the expansion board into an analyzer (LE-3500/LE-2500), the communications line you want to measure is connected using the included probe pod. Since nine kinds of the signal lines can be tested, you can measure various communications: SD, RD, RS, CS, SD_CLK, RD_CLK, external input, trigger input and trigger output. Moreover, you can set the polarity of data and the clock you wish to capture.

Monitoring

In the normal mode (USART), you can make full use of the functions of an analyzer such as the trigger function. Also, by setting the BURST mode on the analyzer, you can measure communication system (clock synchronous communication) which supplies the clock at the time of only transmitting data. That makes it possible to monitor communication that the old protocol analyzers cannot measure. In addition, by setting the I²C mode, you can test the I²C serial communications including the start sequence and stop sequence. Since the translation display is available in I²C, you can efficiently analyze the sequences of Read and Write.

<I2C Measuring Result Screen>

<I2C Translation Screen>

Logic Analyzer

By using the logic analyzer function, you can check the data logic and the timing for capturing the clock in the waveform. Especially, the serial interface between LSI often can be a problem regarding the phase difference and the delay of the clock and data. In this case, the logic analyzer function enables you to analyze by bit timing.

Simulation / Bert

Excepting the BURST mode, using the simulation function enables you to vastly enhance the efficiency of the development and the trouble analysis. In the I²C mode, you can simulate in both the master and the slave. Also, since the bit error rate test (BERT) is available in the normal mode (USART), you can easily test the transmission feature of the device, etc.

Specification

Interface	RS-232C, TTL, I2C
Probe Signal	SD (SDA), RD, RS, CS, EXIN, SDCLK (SCL), RDCLK, Trigger IN, Trigger OUT [Lead Length: 170mm]
Protocol	I2C, Clock SYNK (*1)
Function	Monitor / Simulation /BERT (*2)
Speed (I2C Test)	100Kbps, 400Kbps, 1Mbps
Input Impedance	100K Ohm, (0<=Vin<=5V) Vin max. -25V to +25V
Input Level Threshold	High: Min.2.2V, Low: MAX.0.9V
Output Level Voltage	High: 3.0V, 4.5V, without pull-up (*3), Low: Max.0.5V
Composition	Dedicated expansion board (SB-20N), Relay cable, Probe pod

(*1) Mode for sampling data at all clock edges.
(*2) I²C BERT testing not supported.
(*3) Set from analyzers.