Firmware for High-speed HDLC/SPI
(For LE-8200A/8200)



This expansion firmware increases the baud rates of bit synchronous communications (e.g., HDLC/SDLC/X.25, and CC-Link communications). The firmware processes main measurement items completely with a field programmable gate array (FPGA), thus precisely capturing communications data along with time stamps in 1-μs units.
* From version 2.00(or later), it supports TTL signal level of HDLC/SPI communications measured by LE-8200(A) with TTL expansion kit "OP-SB85/OP-SB85L".

Firmware OP-FW12G
Version 2.00 or later
Version 1.00
RS-422/RS-485HDLC Yes No


  1. Connect the analyzer with a PC by AUX cable or USB cable.
  2. Set the firmware CD-ROM to the PC.
  3. Transfer the firmware using the software included in the CD-ROM.
  4. Once the firmware is installed the analyzer runs in high-speed mode.

< OP-FW12G opening display >

Following is how to change the normal mode and the high-speed mode.
High-speed mode to normal mode : turn on the power by pushing [Shift] and [0].
Normal mode to high-speed mode : turn on the power by pushing [Shift] and [3].

Operating Instructions


Connect to RS-232C port of analyzer using the monitor cable "LE-25M1".


Connect to RS-422/485 line as shown in the following figure by using the terminal block for DSUB 25-pin (LE-25TB) etc. of an option.

Half-duplex 2 (TxD_A), 14 (TxD_B)
7 Connect (GND)
Full-duplex 2 (TxD_A), 14 (TxD_B)
3 (RxD_A), 16 (RxD_B)
7 Connect (GND)

If you need the terminator, turn on by DIP SW on the interface board.


Connect using the optional expansion kit "OP-SB85/OP-SB85L".

■HDLC Monitor

■HDLC Simulation

■SPI Monitor

■SPI Simulation
□Master Mode
Connect SDO(SD) to MOSI, SDI(RD) to MISO, SS(RTS) to SS, and SCK(TXC) to SCK.

■SPI Simulation
□Slave mode
Connect SDO(SD) to MOSI, SDI(RD) to MISO, SS(RTS) to SS, and SCK(TXC) to SCK.


It can monitor ASYNC/HDLC/Profibus-DP (Max 12Mbps) or SPI (Max 20Mbps) at arbitrary speed in real-time. Time stamp resolution that is effective to check the response time is selectable from 1mS/100uS/10uS/1uS. Therefore, it is useful for development and analysis of failures for High-speed communications effectively.

■HDLC/SDLC/X.25 and CC-Link

ID filter that can capture frames only on the specific address (16bits) can be individually specified on the SD and RD side. This improves the efficiency of analysis and data use in the capture memory. At the time of the half-duplex, the frames of specific address can be divided to the SD side, the other frames are sent to the RD side.

< HDLC Setup Screen >

< HDLC Monitoring Screen (normal) >

< HDLC Monitoring Screen (packets) >


There are 4 kinds of SPI transferring timing by clock polarity and clock phase.This products supports all these kinds and monitors SPI communications in most of the SPI devices. Some of the SPI devices transer all frames with low level SS signal. This product can analyze the relationship between transferring commands and data by setting the Frame End Time.

< SPI Setup Screen >

< SPI Monitoring Screen (normal) >

< SPI Monitoring Screen (dump) >


When 2 sets of communication data string up to 8 characters (don’t care and bit mask available) is detected individually or sequentially, or when error (CRC error, abort, short frame) is detected, monitoring action can be stopped automatically.

< Example of Trigger Setup Screen1 >

< Example of Trigger Setup Screen2 >

< Example of Trigger Setup Screen3 >


Simulation function is useful when it is in the early stage of development, and when there are few partner devices to perform high-speed communications. By pressing the corresponded key, 16 kinds of data registered in the transmission data table can be transmitted once or repeatedly. For TTL interface, you can select the output signal level and type that suits to the target circuit. For SPI simulation, it has Master and Slave mode, and able to have the transmission/reception test up to 12Mbps (Master mode).

< SPI Setup Screen >

Support Logic Analyzer function (Ver.2.03 or later)

Logic Analyzer function at max 100MHz sampling speed enables you to analyze timing of high-speed HDLC and SPI signals by digital waveform. It helps you to solve the hardware troubles, and it is also useful for educational purpose for data communication studies.